Conventionally, a computer employing a virtual memory system stores a list called a page table for translating a virtual address (VA) into a physical address (PA) in a main storage (main memory). If the computer refers to the page table in the main storage in every address translation, long time is required, so that the computer normally includes a cache dedicated for address translation called a TLB (Translation-lookaside buffer) in a CPU (Central Processing Unit).
When accessing a memory, an operation unit or an instruction control unit of the computer translates a virtual address into a physical address by the TLB and accesses the memory directly by using the physical address, so that the access speed of the TLB directly influences the speed of the memory access. For increasing the access speed of the TLB, the capacity of the TLB needs to be made small. However, if the capacity is too small, a TLB miss occurs frequently, thereby increasing the access time. On the other hand, if the capacity of the TLB is too large, the time for searching becomes long, which may inhibit improvement of a hardware performance. A technology of configuring the TLB in two levels is often employed as a method for improving the hardware performance while shortening the access time.
The TLB having two levels consists of an MTLB (main TLB) of a large capacity that stores therein address translation pairs transferred from the main storage and an MTLB (micro TLB) of a small capacity that stores therein address translation information that was searched in the past. When performing address translation, the micro TLB searches for an address translation pair (entry) by using a virtual address and a context bit of a request, and a TLB virtual address, a TLB context bit, and page size information registered in the TLB, and translates the virtual address into an absolute address if matching a valid entry.
The page size registered in the TLB is six kinds of 8 KByte, 64 KByte, 512 KByte, 4 MByte, 32 MByte, and 256 MByte (hereinafter, sometimes simply referred to as 8 K, 64 K, 512 K, 4 M, 32 M, and 256 M, respectively). There is a page offset of a virtual address depending on the page size. Therefore, when performing address translation, the micro TLB judges an offset address of the virtual address to be compared based on the page size of a requested entry and removes the offset, thereby performing the address translation searching only with a valid virtual address (see Japanese Laid-open Patent Publication No. 05-225064).
However, in the above conventional technology, a problem arises in that the processing performance degrades because the number of address comparison conditions is large. To specifically explain the problem, as depicted in FIG. 7, an offset corresponding to a page size is added to a search request output from an operation unit or an instruction control unit of a CPU to the micro TLB together with a virtual address. The micro TLB compares the virtual address in which the offset calculated based on the input search request is removed from the search request with the registered virtual address. When they match with each other, the micro TLB responds with an absolute address. The offset added is different depending on the page size, so that the micro TLB includes a comparison circuit, which compares the virtual address calculated by detecting the page size of the input search request and removing the offset, for each page size as depicted in FIG. 8. Consequently, because the number of the address comparison conditions becomes large with respect to the input search request, the processing performance of the micro TLB degrades. FIG. 7 is a schematic diagram for explaining the conventional technology. FIG. 8 is a schematic diagram illustrating an example of an address translation pair searching circuit in the conventional technology.